The present invention is related to an efficient thin-film opto-electronic device on a low-cost Si-containing substrate. of particular interest are opto-electronic devices like solar cells and LED""s.
When analysing the technology progress on solar cells, being one of the opto-electronic devices under consideration, one can observe that an important research effort has been put in the development of solar cells in thin crystalline Si-based layers deposited on Si-containing substrates. It is a common feeling that this technical field remains important towards the future and carries a long-term economical importance. However, thin-film solar cell structures on a Si-containing substrate suffer from an intrinsic lack of light confinement. To assure a sufficiently high efficiency, one has to succeed to increase the light confinement into the thin film and at the same time avoid absorption losses into the substrate. The solution of this problem provides a major opportunity for advances in the efficiency of crystalline Si-based solar cells. Particularly, by collecting and confining the incident light in a small material volume, diffusion length requirements for efficient charge collection are relaxed and the thickness of the active layer in the silicon solar cell can be drastically reduced.
Several solutions have been proposed to introduce or improve light confinement. However all these different solutions have in common that the thin-film material quality is reduced and/or the complexity of the fabrication Process increases. Some of these solutions are:
a) grooving or texturing of the substrate prior to the thin-film deposition (as e.g. in U.S. Pat. No. 4,571,448). This has only limited beneficial results. The first pass of the incoming light is increased but there is no back reflection. Moreover, this solution has a negative influence on the complexity of the fabrication process.
b) deposition of the thin-film on a substrate which has an intermediate oxide layer acting as backside reflector. However, the use of such an oxide implies a lower quality of the deposited material and is technologically complicated.
c) a substrate etch-back can be performed to thin the substrate in order to be able to use the backside of the substrate as a reflector. Such an etch-back process leads to a severely decreased mechanical stability, which is also undesirable.
Independently in another technical field, research is carried out on epitaxial growth on porous Si. An interesting observation is that it is possible to obtain high-quality thin films when depositing Si on a porous Si surface. This has resulted mainly in using this technique for silicon-on-insulator (SOI) applications. For these applications the porous layer is a disposable layer since the porous layer is removed afterwards as e.g. in the United States patent U.S. Pat. No. 5,536,361.
Recently epitaxial growth on porous Si has been applied also in the field of solar cells as in R. Brendel, xe2x80x9cA novel process for ultra-thin monocrystalline silicon solar cells on glassxe2x80x9d, 14th European PV-Conference, Barcelona 1997, pp. 1354-1357. Here, a Si-film is grown on porous Si and transferred afterwards onto another substrate, i.e. a glass substrate. As in the SOI-application, the grown porous Si layer is a disposable layer.
Documents DE-4319413, U.S. Pat. No. 5,696,629 and WO-A-94/29757 disclose an optical component including a multilayer stack of porous silicon layers grown on a silicon substrate. The multilayer stack is serving as a detector, an interference filter or a reflector.
The document JP-02031204 discloses a method for making a III-V group semiconductor solar battery on a silicon substrate. In order to achieve a higher photoelectric conversion efficiency of this solar battery, the surface of the silicon substrate is made porous prior to the growth of the III-V group semiconductor. The higher photoelectric conversion efficiency is achieved by having less transposition, residual stress and lattice defects in the III-V group semiconductor.
An aim of the invention is to achieve light confinement in a crystalline thin-film opto-electronic device being formed on a Si-containing substrate in order to increase the efficiency of this device. Typical thin-film materials are Si, Ge, SiGe and other III-V compound materials.
It is a further aim of the invention to achieve this light confinement without a substantial deterioration of the thin-film material quality and without substantially increasing the process complexity.
In an aspect of the invention a thin-film opto-electronic device on a Si-containing substrate is disclosed. Particularly, this thin film is a crystalline semiconductor layer. The thin film can be for instance single-crystalline or polycrystalline. In order to increase the efficiency of this device a porous layer is applied between the thin-film and the substrate. This porous, preferably silicon, layer has both light reflecting and light diffusing properties thereby giving rise to light confinement in the thin-film. Besides the optical benefits, the porous layer can also act as a barrier layer, which prevents diffusion of impurities from a substrate into the deposited semiconductor layer. This is advantageous especially in the case of low-cost and therefore impure substrates. This barrier layer activity is due to gettering of impurities at the large internal porous surface, but can be a result of other phenomena as well.
Particularly, a thin-film opto-electronic device on a conductive silicon-containing substrate is disclosed comprising:
a porous silicon layer on said substrate, said porous silicon layer having both light diffusing and light reflecting properties;
a non-porous layer on said porous silicon layer; and
at least one first region and at least one second region in said non-porous layer, said first region of a first conductivity type preferably acting as a light absorber, said second region having a conductivity of a second type, different from said first conductivity type, for contacting said thin-film opto-electronic device.
Preferably, said non-porous layer is a non-porous semiconductor layer.
According to one preferred embodiment, said non-porous semiconductor can be a crystalline layer.
According to a second embodiment, said non-porous semiconductor layer can be an elemental layer.
According to a third embodiment, said non-porous semiconductor layer can be made of an element of group IV.
Preferably, said device comprises at least three regions:
a first region of a first conductivity type and having a doping level,
a second region of a second conductivity type within said region, and
a third region of said first conductivity type and being of a higher doping level than the doping level of said first region, said third region not abutting said second region.
Preferably, said porous layer has a gradually changing porosity from on place, preferably the bottom of the layer, to another place, preferably the top of the layer. Said porous layer can also contain a plurality of porous layers with a different porosity.
According to a preferred embodiment, said device can further have a second layer of a porous medium in/or on said non-porous layer.
Said second layer can be a porous silicon layer or a porous dielectric layer.
Said porous dielectric layer can be a silicon nitride layers.
The present invention is also related to the use of a sequence of layers as described hereabove for making a thin film opto-electronic device on a conductive silicon-containing substrate wherein optical confinement is realised.
In a preferred embodiment of the invention, the porous Si layer has a thickness in the range from 0.1 xcexcm to 1 xcexcm. The porosity has a value typically between 20% and 70%. This porosity can be tuned dependent on the desired performance being the overall efficiency of the device. An Increase in porosity yields a better light confinement being beneficial for the efficiency but a decrease in the semiconductor layer material quality being detrimental for the efficiency. Furthermore the porosity can be influenced by the subsequent heat treatments as e.g. during the formation of the semiconductor layer. Particularly if temperatures above about 750xc2x0 C. are applied, volatilisation and coarsening can occur in the porous silicon layer. Examples of semiconductor layers are layers of silicon, Ge, SiGe or other III-V compound materials.
In another embodiment of the invention, the porous silicon layer comprises porous silicon parts and columnar conductive parts, said columnar conductive parts forming conductive connections between the substrate and the semiconductor layer. Particularly, these columnar conductive carts form conductive connections between the substrate and the first region of the semiconductor layer; said substrate having the same conductivity type as said first region, being either n-type or p-type, and said substrate being provided with a contact. The substrate is preferably a highly doped silicon substrate. The columnar parts can also be advantageous to achieve a better crystallinity of the semiconductor layer by providing crystalline growth nuclei.
In another aspect of the invention, a method for fabricating a thin-film opto-electronic device on a conductive silicon-containing substrate is disclosed, comprising the steps of:
a) forming a porous silicon layer on said substrate such that said porous silicon layer acts as a light diffuser and as a Light reflector;
b) growing a non-porous layer, preferably a crystalline layer, on said porous silicon layer, said non-porous layer comprising at least one first region and at least one second region being formed in said non-porous layer, said first region of a first conductivity type acting as a light absorber, said second region of a second conductivity type, different from said first conductivity type, for contacting said thin-film opto-electronic device.
The quality of the non-porous layer grown depends on both the porosity of the initial porous layer and the growth temperature. Particularly if temperatures above about 750xc2x0 C. are applied, volatilisation and coarsening can occur in the porous silicon layer.
In another embodiment of the invention, the porosity of the initial porous layer is in the range from 20% to 70%, while the temperature during the subsequent growing step is preferably below about 750xc2x0 C. The porous silicon layer can be formed by exposing the substrate to an electrochemical treatment or a chemical treatment or spark erosion.
In another embodiment of the invention, the porous Si layer is formed by an electrochemical treatment, particularly, by electrochemical anodisation, e.g. in a HF-based electrolyte. The obtained thickness of the porous silicon layer depends on the anodisation time and is typically in the range from 0.1 xcexcm to 1 xcexcm. The substrate is preferably a highly doped Si substrate having either a n-type or a p-type conductivity. The porous silicon layer formed can comprise porous silicon parts and columnar conductive parts, said columnar conductive parts forming conductive connections between the substrate and the first region of the non-porous layer; said substrate and said first region having the same conductivity type.
In another embodiment of the invention, prior to the formation of the porous silicon layer a patterned mask layer is formed on the substrate to thereby define at least one first area and at least one second area in the substrate, said first area being uncovered, said second area being covered with said mask layer; thereafter said porous silicon layer is formed on said first area and said mask layer is removed from said second area; thereafter a non-porous layer is grown on said second area and on said porous silicon layer thereby creating said columnar conductive parts.
In another embodiment of the invention a method is disclosed wherein the non-porous layer is a Si or a Ge or a SiGe or a III-V compound layer being grown by means of chemical vapour deposition or physical vapour deposition or molecular beam epitaxy.
In another embodiment of the invention a method is disclosed wherein the substrate is not used for contacting the device. Particularly, the substrate can be lowly doped or not doped and/or isolated from the semiconductor layer. Instead, according to this method, at least one third region is formed in said first region for contacting said first region, said third region being isolated from said second region and having the same conductivity type as said first region.